1. Field of the Invention
The present invention relates to a bidirectional shift register capable of changing the output sequence of pulses and an image display device using the same to drive each of scanning lines.
2. Description of the Related Art
The improvement in resolution of an image display device is realized by the improvement in arrangement density of pixels of a display part. Along with that, the arrangement pitch of various signal lines to supply signals to pixel circuits becomes narrow. Gate lines provided as scanning lines of pixels are connected to a gate line drive circuit on the side of a display area. The gate line drive circuit includes a shift register to sequentially output voltages, which enable writing of data to the pixel circuits, to the respective scanning lines. Along with the increase in resolution, the reduction of a unit register circuit constituting each stage of the shift register is also required.
In general, voltages to the gate lines are applied in a single direction (forward direction) and in the sequence from the upper to the lower side of an image correspondingly to the input sequence of image data in a vertical scanning direction. If the shift register can be driven in both directions (not only in a forward direction but also in a backward direction), the input image data can be written to the pixel circuits in the sequence of scanning lines from the lower to the upper side. By this, as compared with a structure in which a frame memory or the like for buffering image data is provided and the sequence of the image data is changed there, the direction of the image to be displayed can be changed by a simple structure.
The shift register used in the gate line drive circuit or the like includes a plurality of cascade-connected unit register circuits, and basically, the unit register circuits at respective stages sequentially output a pulse once from one end to the other end of the column of the unit register circuits in synchronization with vertical scanning or the like.
FIG. 17 is a circuit view showing a basic structure of a unit register circuit (see JP 2004-157508A). An output transistor M1 is connected between an output terminal (GOUT[n]) of an n-th unit register circuit and a clock signal source CK. Besides, a transistor M2 is connected between the terminal (GOUT[n]) and a power source VOFF. FIG. 18 is a signal waveform view for explaining the operation of the unit register circuit (see JP 2009-272037A). When an output pulse GOUT[n−1] of the preceding stage is inputted to the unit register circuit, a node N3 (one end of a capacitor C) connected to the gate of M1 is connected to a power source VON, and the potential at the node N3 is raised to a High (H) level which is a potential to turn on the transistor. Besides, when N3 is at the H level, a node N4 is connected to the power source VOFF, and is set to a Low (L) level which is a potential to turn off the transistor, and M2 is placed in the off state. In this way, the unit register circuit is placed in the set state, and when the clock signal CKV (CK) changes from the L level to the H level, the potential at N3 is further raised through the capacitor C connected between the source and the gate of M1, and the H level of the clock signal CKV appears at the output GOUT[n].
On the other hand, when the clock signal CKV changes from the H level to the L level, the potential at N3 is reduced, and the voltage of the output GOUT[n] is also reduced. At this time, a pulse is generated at the latter stage output signal GOUT[n+1] in synchronization with the rise of the clock signal CKVB to the (n+1)-th stage, and is inputted to the n-th unit register circuit. The pulse of GOUT[n+1] decreases the potential at N3 and raises the potential at N4 to place M2 in the on state, and the output terminal is connected to VOFF. By these operations, the output of the pulse of the output signal GOUT[n] is ended.